A team, led by MSE's Professor Lane Martin and in collaboration with MSE's Professor R. Ramesh and collaborators at the Intel Corporation, have identified one route to potentially reduce the energy of next-generation memory and logic devices. The key was developing an approach to synthesize an "ideal" thin-layer version of a well-known ferroelectric material whose properties are exactly what’s needed for next-generation devices. More information on this work can be found here.